Difference Between SRAM and DRAM

SRAM and DRAM are the modes of integrated-circuit RAM where SRAM uses transistors and latches in construction while DRAM uses capacitors and transistors. These can be differentiated in many ways, such as SRAM is comparatively faster than DRAM; hence SRAM is used for cache memory while DRAM is used for main memory.

RAM (Random Access Memory) is a kind of memory which needs constant power to retain the data in it, once the power supply is disrupted the data will be lost, that’s why it is known as volatile memory. Reading and writing in RAM is easy and rapid and accomplished through electrical signals.

Content: SRAM Vs DRAM

1. Comparison Chart
2. Definition
3. Key Differences
4. Conclusion

Comparison Chart

Basis for comparison	SRAM	DRAM
Speed	Faster	Slower
Size	Small	Large
Cost	Expensive	Cheap
Used in	Cache memory	Main memory
Density	Less dense	Highly dense
Construction	Complex and uses transistors and latches.	Simple and uses capacitors and very few transistors.
Single block of memory requires	6 transistors	Only one transistor.
Charge leakage property	Not present	Present hence require power refresh circuitry
Power consumption	Low	High

Definition of SRAM

SRAM (Static Random Access Memory) is made up of CMOS technology and uses six transistors. Its construction is comprised of two cross-coupled inverters to store data (binary) similar to flip-flops and extra two transistors for access control. It is relatively faster than other RAM types such as DRAM. It consumes less power. SRAM can hold the data as long as power is supplied to it.

 Working of SRAM for an individual cell:

To generate stable logic state, four transistors (T1, T2, T3, T4) are organized in a cross-connected way. For generating logic state 1, node C1 is high, and C2 is low; in this state, T1 and T4 are off, and T2 and T3 are on. For logic state 0, junction C1 is low, and C2 is high; in the given state T1 and T4 are on, and T2 and T3 are off. Both states are stable until the direct current (dc) voltage is applied. The SRAM address line is operated for opening and closing the switch and to control the T5 and T6 transistors permitting to read and write. For read operation the signal is applied to these address line then T5 and T6 gets on, and the bit value is read from line B. For the write operation, the signal is employed to B bit line, and its complement is applied to B’.

Definition of DRAM

DRAM (Dynamic Random Access Memory) is also a type of RAM which is constructed using capacitors and few transistors. The capacitor is used for storing the data where bit value 1 signifies that the capacitor is charged and a bit value 0 means that capacitor is discharged. Capacitor tends to discharge, which result in leaking of charges.

The dynamic term indicates that the charges are continuously leaking even in the presence of continuous supplied power that is the reason it consumes more power. To retain data for a long time, it needs to be repeatedly refreshed which requires additional refresh circuitry. Due to leaking charge DRAM loses data even if power is switched on. DRAM is available in the higher amount of capacity and is less expensive. It requires only a single transistor for the single block of memory.

Working of typical DRAM cell:

At the time of reading and writing the bit value from the cell, the address line is activated. The transistor present in the circuitry behaves as a switch that is closed (allowing current to flow) if a voltage is applied to the address line and open (no current flows) if no voltage is applied to the address line. For the write operation, a voltage signal is employed to the bit line where high voltage shows 1, and low voltage indicates 0. A signal is then used to the address line which enables transferring of the charge to the capacitor.

When the address line is chosen for executing read operation, the transistor turns on and the charge stored on the capacitor is supplied out onto a bit line and to a sense amplifier. The sense amplifier specifies whether the cell contains a logic 1 or logic 2 by comparing the capacitor voltage to a reference value. The reading of the cell results in discharging of the capacitor, which must be restored to complete the operation. Even though a DRAM is basically an analog device and used to store the single bit (i.e., 0,1).

Conclusion

DRAM is descendent of SRAM. DRAM is devised to overcome the disadvantages of SRAM; designers have reduced the memory elements used in one bit of memory which significantly reduced the DRAM cost and increased the storage area. But, DRAM is slow and consumes more power than SRAM, it needs to be refreshed frequently in few milliseconds to retain the charges.