RISC and CISC are the characterizations of computer instruction sets which is a part of computer architecture; they differ in complexity, instruction and data formats, addressing modes, registers, opcode specifications, and flow control mechanisms, etc.
When a machine is programmed, the programmer uses some particular primitive commands or machine instruction these are generally known as instruction set of a computer.
Content: RISC Vs CISC
|Basis for comparison||RISC ||CISC|
|Instruction formats||fixed (32-bit) format||Varying formats (16-64 bits each instruction).|
|Addressing modes used||Limited to 3-5||12-24|
|General purpose registers used||32-192||8-24|
|Memory inferences||Register to register||Memory to memory
|Cache design||Split data cache and instruction cache.||Unified cache for instructions and data.|
|Clock rate||50-150 MHz ||33-50 MHz|
|Cycles Per Instruction ||Single cycle for all instructions and an average CPI < 1.5.||CPI between 2 and 15.|
|CPU Control||Hardwired without control memory.||Microcoded using control memory (ROM).|
Definition of RISC
Reduced instruction set computers (RISC) instruction sets typically hold less than 100 instructions and use fixed instruction format (32 bits). It uses few simple addressing modes. Register-based instructions are used which means register to register mechanism is employed. LOAD/STORE are the only independent instructions for accessing memory.
To improve the speed of context switching, a large register file is used. The simplicity of instruction sets resulted in the implementation of whole processors on a single VLSI chip. The additional benefits are higher clock rate, lower CPI that govern high MIPS ratings on available RISC/ superscalar processors.
Definition of CISC
Complex instruction set computers (CISC) instruction set contains around 120 to 350 instructions. It uses variable instruction /data formats but a small set of general purpose registers, i.e. 8-24. The reason for large instruction sets is the use of variable format instructions. A large number of memory reference operations are executed by using an enormous number of addressing modes.
CISC architecture straightly employs the HLL statements in hardware/firmware. Unified cache is used in traditional CISC architecture which contains both data and instructions and uses the common path.
Key Differences Between RISC and CISC
- In RISC the instruction set size is small while in CISC the instruction set size is large.
- RISC uses fixed format (32 bits) and mostly register-based instructions whereas CISC uses variable format ranges from 16-64 bits per instruction.
- RISC uses a single clock and limited addressing mode (i.e., 3-5). On the other hand, CISC uses multi-clock 12 to 24 addressing modes.
- The number of general purpose registers that RISC uses ranges from 32-192. On the contrary, CISC architecture uses 8-24 GPR’s.
- Register-to-register memory mechanism is used in RISC with independent LOAD and STORE instructions. In contrast, CISC uses memory to memory mechanism for performing operations, furthermore, incorporated LOAD and STORE instructions.
- RISC has split data and instruction cache design. As against, CISC uses unified cache for data and instructions, although latest designs also use split caches.
- Most of the CPU control in RISC is hardwired without having a control memory. Conversely, CISC is microcoded and uses control memory (ROM), but modern CISC also uses hardwired control.
CISC instructions are complex and tend to slower than RISC but utilizes fewer cycles with fewer instructions.